Computer Architecture Senior

Both fixed and variable length decode identically, differing only in the memory they use.

Fixed length improves code density while variable length is simpler and faster to decode.

Variable length eases pipelining while fixed length always yields the most compact code.

Fixed length eases decoding but wastes space; variable length packs code but decodes slower.

Microcode breaks complex instructions into simple micro-ops the core executes efficiently.

Microcode is firmware on disk that boots the processor before any instructions can run.

Microcode is a cache layer that stores decoded instructions to skip fetching them again.

Microcode is the compiler pass that converts source code into machine instructions for x86.

VLIW schedules parallel operations in hardware, while superscalar finds parallelism in the compiler.

VLIW executes one operation per cycle strictly, while superscalar runs several threads concurrently.

VLIW reorders memory accesses dynamically, while superscalar issues instructions strictly in order.

VLIW schedules parallel operations in the compiler, while superscalar finds parallelism in hardware.

Use fixed-point for wider dynamic range and cheaper storage, trading away deterministic rounding behavior.

Use fixed-point for larger exponent handling and speed, trading away compact operand encoding widths.

Use fixed-point for automatic scaling and higher accuracy, trading away simpler integer arithmetic units.

Use fixed-point for deterministic precision and simpler, faster arithmetic, trading away dynamic range.

Nearest (ties to even), toward zero, toward +∞, and toward −∞; the mode controls how much error accumulates.

Nearest, floor, ceiling, and modulo rounding; the mode mainly affects arithmetic speed rather than accuracy.

Truncate, round half up, round half down, and random rounding; choosing a mode forces the total error to zero.

Banker's, statistical, exact, and lossless rounding; picking one guarantees results identical to real arithmetic.

The ROB schedules ready instructions to execution units out of order and lets each one commit immediately as soon as it finishes.

The ROB holds finished instructions in program order and commits their results in that order even though they executed out of order.

The ROB stores branch predictions in order and discards them once the correct execution path through the program has been resolved.

The ROB caches memory operands in program order so that load and store instructions can bypass the slower data cache entirely.

It maps architectural registers onto a larger physical set, so name-reuse WAR/WAW dependencies vanish and more instructions run in parallel.

It reorders instructions that share a register name at compile time, so the WAR/WAW pairs never appear together inside the pipeline.

It stalls instructions that reuse a register name until the prior writer commits, so the WAR/WAW ordering is preserved and made safe.

It forwards each result directly between stages, so the reused register name is never read early and every WAR/WAW hazard is bypassed.

Out-of-order skips stalled instructions permanently, using a write buffer to discard results that arrive later than expected

Out-of-order fetches instructions backwards from memory, using a branch predictor to reorder the whole instruction stream

Out-of-order runs ready instructions early despite program order, using a reorder buffer to retire results in order

Out-of-order runs instructions on multiple cores at once, using a shared cache to keep every result globally consistent

It hides latency by executing independent work early, while in-order retirement commits results and exceptions in program order

It saves power by pausing idle units early, while the memory controller replays each store to restore its correct ordering

It boosts throughput by duplicating registers early, while the compiler inserts barriers that force results back into order

It raises clock speed by shortening pipeline stages, while a checksum unit verifies that outputs match the original ordering

The compiler statically orders instructions so hardware never needs to stall waiting on any pending operand values

Reservation stations track operands and register renaming removes false dependencies so instructions issue when ready

A lookahead unit precomputes all branch targets so dependent instructions can be dispatched together far ahead of time

A central queue forces every instruction to wait for the previous one to fully commit before its operands are read

Inclusive stores each line in only a single level; exclusive duplicates every line across all levels to speed up coherence

Inclusive allows only read data to be cached; exclusive allows only writes, splitting the hierarchy strictly by access type

Inclusive keeps lower-level data duplicated in higher levels; exclusive holds each line in only one level to save capacity

Inclusive bypasses the last-level cache entirely; exclusive routes all data through it to keep every level fully synchronized

The TLB sits after the L1 cache, so both VIPT and PIPT tag the cache with virtual addresses

VIPT waits for the TLB to finish translating before it can index and compare the cache tags

PIPT indexes with virtual bits while the TLB translates in parallel, then compares virtual tags

VIPT indexes with virtual bits while the TLB translates in parallel, then compares physical tags

It walks the multi-level page table, using address bits to index each level down to the final frame

It searches the L2 cache for the translation, using address bits to locate the matching frame entry

It walks the multi-level page table, storing every possible entry so no memory is ever left unused

It interrupts the OS, which linearly scans a single flat table to find the correct frame number

Both translate the address first, but VIPT is faster because it stores larger cache line blocks

PIPT overlaps cache indexing with TLB translation, while VIPT must translate before it can index

VIPT overlaps cache indexing with TLB translation, while PIPT must translate before it can index

VIPT and PIPT both index after translation; the difference is only in how the tags are stored

Consecutive addresses are compressed before storage across banks and channels so more data fits, increasing the usable bandwidth.

Consecutive addresses are duplicated across multiple banks and channels so failed reads can retry elsewhere, improving reliability.

Consecutive addresses are grouped into one bank and channel so accesses stay local, reducing latency but limiting total bandwidth.

Consecutive addresses are spread across multiple banks and channels so accesses overlap in parallel, raising effective bandwidth.

UMA scales better for large servers because remote access is free, while NUMA forces every access to go through one shared controller

UMA and NUMA both provide uniform latency, but NUMA simply adds more channels, so data placement never affects performance at all

UMA gives each processor its own local memory bank, while NUMA shares one uniform memory pool with equal latency for all cores

UMA gives all processors uniform memory latency, while NUMA has faster local memory, so software should keep data near the accessing CPU

MESI marks each line Managed, Exclusive, Stored, or Idle so multiple cores can freely write the same line while hardware merges the written results.

MESI copies every write immediately to all caches at once so every core keeps an identical full duplicate of the shared main memory contents.

MESI locks the entire cache during any write so that no other core can read memory until the writing core has fully flushed its pending changes.

MESI marks each line Modified, Exclusive, Shared, or Invalid so only one core writes a line and others always observe consistent, non-stale data.

Independent variables placed on the same cache line cause cross-core invalidations on writes; align or pad data to separate lines to prevent it.

Two cores read the same shared variable and stall on its lock; assign each core its own private copy of the variable to remove the contention.

A cache line is evicted too early because of limited capacity; increase the cache associativity so that hot lines are retained longer for reuse.

One core writes memory another has cached as valid data; disable the cache entirely on that region so all accesses go straight to main RAM.

It pauses all other cores until the current core completes, ensuring that only one memory operation is ever in flight at any given moment.

It enforces an ordering constraint on memory operations, stopping hardware or compiler from reordering loads and stores across the barrier.

It flushes the entire cache hierarchy back to main memory, guaranteeing every core immediately sees a fully coherent global view of memory.

It converts weakly-ordered accesses into atomic transactions, so that grouped reads and writes always commit together as one indivisible unit.

Snooping stores data only in main memory and suits small systems; directory-based caches everything locally and suits very large-scale systems.

Snooping keeps a central table of all sharers and suits large systems; directory-based broadcasts on a shared bus and suits only smaller systems.

Snooping broadcasts coherence traffic on a shared bus and suits small systems; directory-based tracks sharers in a directory and scales larger.

Snooping requires software to manage coherence and suits small systems; directory-based lets hardware manage it and suits many-core systems best.

Owned forces an immediate writeback to memory whenever any core reads that shared cache line

Owned lets one cache hold dirty data and supply it to others without writing back to memory

Owned marks a line as exclusive and clean so writes proceed with no bus transaction at all

Owned allows two separate caches to both write the same line at once via a locked bus cycle

CAS spins in software rereading a value until two consecutive reads return identical results

CAS disables all interrupts while it reads then writes a value, so no other core can interfere

CAS locks the whole cache line permanently until the owning thread explicitly releases it

CAS atomically compares a location to an expected value and updates it only if they match

Sequential consistency permits any reordering while relaxed models strictly forbid all reordering

Sequential consistency preserves program order globally; relaxed models let loads and stores reorder

Sequential consistency requires atomics whereas relaxed ordering by itself guarantees cache coherence

Sequential consistency applies only to caches while relaxed models apply only to main memory access

They encrypt all guest memory pages transparently to isolate virtual machines from one another

They emulate privileged instructions in microcode so the hypervisor never has to intervene at all

They provide extra general-purpose registers dedicated to storing each guest operating system

They add a new CPU execution mode that traps privileged guest instructions to the hypervisor

It assigns interrupt priorities to devices so passthrough guests receive their events in fair order

It remaps and restricts device DMA addresses, isolating devices and enabling safe passthrough

It translates virtual addresses for the CPU cores while devices access physical memory directly

It caches device I/O requests in a buffer to speed up repeated DMA transfers into memory

Operating systems could not schedule threads fast enough, so hardware vendors offloaded that work onto multiple parallel cores

Memory latency stopped improving, so extra cores were added purely to hide the growing gap between CPU and RAM speeds

Silicon transistors reached their absolute physical size limit, making any further single-core frequency gains impossible to achieve

Power and heat scale steeply with frequency and voltage, so adding cores became more efficient than pushing clocks higher

The CPU runs untrusted code with elevated kernel privileges, allowing that code to directly read protected memory regions without any checks

The CPU predicts branches wrongly and permanently corrupts register state, which attackers then read out through timing measurements on the bus

The CPU executes instructions ahead of a branch, and side effects on the cache can leak data even after the results are discarded

The CPU reorders memory writes so that stale values remain visible, letting one process silently overwrite another process's private data

Flash can only erase in large blocks, so updating small data forces rewriting whole blocks, causing more physical writes than requested

Flash lacks a spinning platter, so the controller must recompute parity for every logical page and store multiple redundant copies of it

Flash cells slow down as they wear, so the controller duplicates each write across several chips to preserve data before the cells fail

Flash reads are destructive, so every read operation triggers an immediate rewrite of the same page back into the original memory location

Inference must stream huge weight tensors from memory per token, so the GPU idles waiting on data rather than saturating its compute units

The batch size is too large for cache, so the GPU repeatedly recomputes activations rather than fetching them from the slower main memory

The model has so many layers that the GPU runs out of arithmetic units, so extra weights must queue in memory until compute frees up again

Floating-point precision is too high, so the GPU spends most cycles converting formats instead of moving the weight tensors through its cores

It assumes problem size grows with processors, so the parallel share expands and speedup scales nearly linearly.

It assumes communication overhead is negligible, so a fixed workload can be split among unlimited processors freely.

It assumes each processor runs at higher clock speed, so total throughput rises faster than Amdahl's fixed model.

It assumes the serial fraction shrinks to zero with more processors, so speedup grows without any practical bound.

It uses a single parity bit per word that flags any error and then rereads the location until the value stabilizes.

It stores a running checksum per word and, when it differs, recomputes the entire block from surrounding cells.

It duplicates every stored byte and compares copies, so any mismatch is rewritten from the known-good backup copy.

It adds redundant parity bits whose syndrome pinpoints a flipped bit's position, correcting single-bit errors.

Chip cost halves as transistors shrink; its breakdown raised fabrication expense, so vendors froze clock frequency

Transistor count doubles as transistors shrink; its breakdown ended density gains, forcing lower clock frequency

Cache latency stays constant as transistors shrink; its breakdown slowed memory, limiting achievable clock frequency

Power density stays constant as transistors shrink; its breakdown made power per area climb, capping frequency

A four-state counter flips on every outcome, so a single anomalous branch is corrected faster than a slow 1-bit scheme

A four-state counter stores two target addresses, so a single anomalous branch still finds a cached path without stalling

A four-state counter averages the last two outcomes, so a single anomalous branch is smoothed out into one steady guess

A four-state counter needs two consecutive misses to flip, so a single anomalous branch does not cause two mispredicts

A table mapping targets to counters, letting fetch bias toward the most frequently taken path before decoding

A queue holding recently fetched instructions, letting fetch replay them quickly when a branch resolves as taken

A cache mapping branch addresses to targets, giving the next fetch address early before the branch is decoded

A cache mapping branch addresses to outcomes, telling fetch whether a branch will be taken before it is decoded