Computer Architecture Mid

RISC always uses fewer registers; x86 adopted this to simplify its backward-compatible assembly.

RISC has more instructions overall; x86 chips now emulate them fully in a dedicated microcode ROM.

RISC uses simple fixed-length instructions; x86 decodes complex instructions into simpler internal micro-ops.

RISC runs at higher clock speeds; x86 shifted internally to reduce total transistor count and cost.

The mismatch between CPU and disk speeds stalls programs; caches and prefetching hide this latency fully.

The fixed instruction width wastes memory bandwidth badly; caches and prefetching compress the code stream.

The single shared path between CPU and memory limits throughput; caches and prefetching cut accesses.

The limited number of CPU registers forces spills to memory; caches and prefetching add register banks.

Harvard uses one memory for everything faster; Modified Harvard adds a second slower memory for backups.

Von Neumann needs two clocks per access always; Modified Harvard runs both instruction fetches in parallel.

Von Neumann shares one memory for code and data; Modified Harvard splits caches but shares main memory.

Von Neumann splits code and data buses; Modified Harvard merges them to reduce total pin count needs.

ISA is the physical chip layout; microarchitecture is the abstract model, so the same code runs slowly.

ISA is the instruction contract; microarchitecture is how it's built, so implementations differ in speed.

ISA defines clock frequency limits; microarchitecture defines the software, so performance varies by compiler.

ISA is the operating system layer; microarchitecture is the transistor process, so newer nodes run faster.

64-bit ISAs guarantee out-of-order execution support, mainly improving branch prediction accuracy overall.

64-bit ISAs expose more and wider registers, easing register pressure and enabling larger operations.

64-bit ISAs double the clock rate and cache size, mainly cutting the number of pipeline stall cycles.

64-bit ISAs add fixed-length instructions and remove microcode, mainly simplifying the instruction decoder.

CISC favors simple uniform instructions and lower power, so it dominates the small mobile device market.

RISC favors complex multi-step instructions and compatibility, so servers keep choosing it for raw speed.

RISC favors variable-length dense encoding and legacy support, giving it a clear edge in energy per task.

RISC favors simple uniform instructions and power efficiency, winning in mobile and now dense servers.

Every arithmetic instruction reads and writes memory without using any registers at all.

Arithmetic instructions may read memory operands directly but cannot write to memory.

Only load and store instructions touch memory; arithmetic works purely on registers.

Loads and stores are combined with arithmetic into single instructions for operands.

Stack machines address operands explicitly; modern CPUs use them for simpler compact code.

Stack machines keep operands in named registers; modern CPUs prefer them for easy decoding.

Register machines push operands onto a stack; modern CPUs avoid them due to complexity.

Register machines address operands explicitly; modern CPUs use them for speed and reordering.

Opcode names the operation, operand fields name the data; encoding sets code density and decode speed.

Opcode names the register, operand fields name the address; encoding sets cache hit rates and latency.

Opcode names the pipeline stage, operand fields name the ports; encoding sets clock frequency and power.

Opcode names the data type, operand fields name the offsets; encoding sets branch prediction accuracy.

The stack saves return addresses and registers; a calling convention defines argument and register rules.

The stack saves cache lines and page tables; a calling convention defines interrupt and priority rules.

The stack saves opcode fields and flags; a calling convention defines memory alignment and paging rules.

The stack saves branch targets and counters; a calling convention defines pipeline and hazard rules.

They round toward zero by default, so bias occurs; IEEE-754 stores flag, magnitude, and length fields.

They lack an exact binary form, so rounding occurs; IEEE-754 stores sign, exponent, and mantissa.

They exceed the register width limit, so truncation occurs; IEEE-754 stores base, offset, and remainder.

They use decimal not binary encoding, so overflow occurs; IEEE-754 stores digit, scale, and precision.

Signed values reserve an extra bit outside the word, so they occupy a wider register than unsigned values do.

The ALU tags every value with a type at load time, and each unit reads that tag before it operates on it.

A dedicated sign flag inside each register marks whether the value stored there should be treated as signed.

The bits are identical; the chosen instructions (signed vs unsigned compares, sign vs zero extension) fix the interpretation.

NaN is max exponent with zero mantissa; infinity is max exponent with nonzero mantissa; subnormals use a max exponent field throughout.

Infinity is zero exponent with max mantissa; NaN is zero exponent with zero mantissa; subnormals are encoded using only the sign bit.

Subnormals are max exponent with zero mantissa; infinity uses a zero exponent; NaN is any value whose sign bit has been set to one.

Infinity is max exponent with zero mantissa; NaN is max exponent with nonzero mantissa; subnormals are zero exponent with nonzero mantissa.

The exponent is stored in two's complement, and the bias corrects the sign so the hardware can add exponents faster.

A fixed constant is added to the exponent so it is stored unsigned, letting plain integer comparison order floats correctly.

A fixed constant is subtracted from the mantissa so that very small numbers can be encoded without losing precision bits.

A scaling factor multiplies the exponent so that one shared encoding can cover both single and double precision formats.

A latch is level-sensitive while a flip-flop is edge-triggered, so flip-flops sample data at defined clock edges

A latch is asynchronous while a flip-flop is combinational, so flip-flops react faster to input changes

A latch is edge-triggered while a flip-flop is level-sensitive, so flip-flops hold data during clock pulses

A latch stores multiple bits while a flip-flop stores one bit, so flip-flops save area in register files

The time a register needs to reset its state; the total gate count sets the achievable clock period

The time a signal stays stable at a gate; the shortest such path sets the maximum clock period

The time between two consecutive clock edges; the average path length sets the usable clock period

The time for a signal to travel through logic; the longest such path sets the minimum clock period

It synchronizes state updates across elements; skew is the difference in clock arrival times between them

It selects which instruction executes next in order; skew is the delay added by a mispredicted branch path

It counts the cycles used by each executed instruction; skew is the gap between issued and retired counts

It supplies operating power to the logic elements; skew is the variation in voltage delivered to each one

Hardwired executes only reduced instructions directly; microprogrammed executes only complex ones in software

Hardwired decodes instructions during compilation; microprogrammed decodes them entirely at runtime instead

Hardwired generates control signals with fixed logic gates; microprogrammed reads them from control memory

Hardwired reads control signals from stored memory; microprogrammed generates them with fixed logic gates

Single-cycle overlaps several instructions per cycle; multi-cycle issues only one instruction across many cycles

Single-cycle runs each instruction in one long cycle; multi-cycle splits work into shorter cycles reusing units

Single-cycle uses microcode for each cycle step; multi-cycle uses hardwired logic to finish in one fixed cycle

Single-cycle splits work into shorter cycles reusing units; multi-cycle runs each instruction in one long cycle

Data, control, and cache hazards; forwarding flushes the pipeline and refetches the stalled dependent instruction from main memory.

Structural, logical, and input/output hazards; forwarding duplicates the register file so two stages can read one value.

Timing, memory, and branch hazards; forwarding delays the dependent instruction until the register file has finally been updated.

Structural, data, and control hazards; forwarding routes an execution result directly to a later instruction's input before write-back.

Running independent instructions on separate cores in parallel raises throughput while the single-core latency of each instruction is unchanged.

Caching recently used results lets instructions skip stages, which increases throughput and simultaneously lowers each instruction's latency.

Overlapping stages of multiple instructions raises completed-instructions-per-cycle while each instruction's own end-to-end latency stays roughly the same.

Executing each instruction faster shortens its latency, and the faster instructions naturally raise the overall throughput of the pipeline.

It renames the destination register so the reader and writer no longer share a name and can run in either order.

It stalls the dependent instruction for several cycles until the produced value is safely committed into the register file.

It reorders the two instructions so the reading instruction executes fully before the writing instruction ever enters the pipeline.

It routes a result from a later pipeline stage straight to a dependent instruction's input, avoiding the wait for write-back.

Per-instruction latency usually rises slightly while throughput improves thanks to a higher achievable clock frequency.

Latency stays fixed while throughput falls because deeper pipelines suffer many more structural resource hazards.

Per-instruction latency falls sharply while throughput drops because each stage now performs far less useful work.

Both latency and throughput improve equally since more stages mean more instructions finish in every clock cycle.

A bubble is a mispredicted branch that flushes the pipeline; stalling avoids all penalties while prediction guarantees maximum throughput.

A bubble is an injected no-op that stalls flow; stalling wastes cycles reliably while prediction risks a costly flush when it is wrong.

A bubble is an extra execution stage added for hazards; stalling raises the clock rate while prediction lowers it and adds complexity.

A bubble is a cache miss that halts fetch; stalling always beats prediction because prediction can never recover the lost cycles at all.

A superscalar issues multiple instructions per cycle via duplicated units, while a simple pipeline issues one per cycle

A superscalar always executes strictly in order, while a simple pipeline reorders instructions to fill more slots per cycle

A superscalar runs at a much higher clock rate, while a simple pipeline compensates by widening its data path per cycle

A superscalar removes the pipeline stages entirely, while a simple pipeline overlaps stages of one instruction per cycle

Write-through skips the cache completely; write-back stores data twice to guarantee memory always stays consistent

Write-through updates memory on every write; write-back defers writes until eviction, reducing memory traffic

Write-through updates only the cache line; write-back copies the entire cache to memory on every single store

Write-through buffers writes until a flush; write-back writes to memory immediately for maximum data durability

Direct-mapped has slow hits but few misses; fully-associative raises misses but is faster; set-associative worsens both

Direct-mapped has fast hits but more misses; fully-associative lowers misses but is slower; set-associative balances both

Direct-mapped has slow hits and many misses; fully-associative fixes both; set-associative offers no real advantage at all

Direct-mapped has fast hits and few misses; fully-associative also has fast hits; set-associative is slower on every access

Compulsory misses occur on first access to a block; increasing associativity fully eliminates them from the cache

Capacity misses occur when the working set fits; shrinking the block size lets more distinct lines coexist in it

Conflict misses occur from a cold cache at startup; prefetching every block ahead of time removes each of them

Conflict misses occur when too many blocks map to one set; adjusting data layout or padding spreads accesses out

AMAT = hit time + miss rate × miss penalty, where each level's miss penalty is the AMAT of the next lower level

AMAT = miss rate × (hit time + miss penalty), computed independently per level and then averaged across every level

AMAT = hit time + miss penalty − miss rate, where the miss penalty stays fixed as the main memory latency throughout

AMAT = hit time × miss rate + miss penalty, summed once over all levels using only the last level's global miss rate

True LRU is trivial in hardware since only one counter per cache is needed, so it is always chosen over random

FIFO always outperforms LRU on real workloads, so true LRU is avoided purely because of its worse hit rates

True LRU must track full recency order per set, costing bits and logic, so hardware uses cheaper approximations

Random needs the most storage of the three, so designers pick true LRU to save area despite the timing penalty

Write-allocate applies only to read misses; no-write-allocate applies only to write hits within a write-back cache line

Write-allocate flushes the whole set on a miss; no-write-allocate keeps the set intact and stalls the pipeline instead

Write-allocate loads the block into the cache on a miss; no-write-allocate writes straight to memory without loading

Write-allocate writes only to memory on a miss; no-write-allocate loads the block first then updates it in the cache

A unified cache holds only data, and L1 splits so instructions can bypass coherence traffic between the core caches

A split cache keeps instructions and data separate, letting fetch and load happen at once without structural hazards

A split cache uses one large port shared by both, and L1 splits so the tag array can be indexed with fewer bits

A split cache stores both streams together, and L1 splits it mainly to double the total capacity of the fast cache

The offset selects the set to probe, the index identifies the block, and the tag selects a byte inside that one block

The tag selects a byte within a block, the offset selects the set, and the index identifies the block within that set

The index selects a byte within a block, the tag selects the set, and the offset identifies the block within that set

The offset selects a byte within a block, the index selects the set, and the tag identifies the block within that set

They compress cache lines on the fly; hardware prefetchers detect duplicate blocks so more data fits near the core

They evict stale data ahead of time; hardware prefetchers scan the tag array to free sets before a miss can occur

They reorder memory writes for locality; hardware prefetchers batch stores together to reduce total bus transactions

They fetch data before it is requested; hardware prefetchers detect access patterns to overlap fetches with compute

It caches recent memory blocks; a miss triggers a page-table walk, while a page fault means the page is not in RAM

It caches address translations; a miss means the page is not in RAM, while a page fault triggers a page-table walk

It buffers pending writes; a miss stalls the CPU, while a page fault evicts a line from the L2 cache entirely

It caches address translations; a miss triggers a page-table walk, while a page fault means the page is not in RAM

The TLB fetches the missing page from disk automatically without any operating-system involvement

The MMU raises a trap, and the OS handler loads the page from disk and updates the page table

The MMU flushes the TLB, evicts a cache line, and the branch predictor reroutes the pipeline flow

The CPU invalidates its caches and keeps retrying the instruction until the page appears in memory

It splits the address into a tag and index, looks up the cache, then appends the remaining offset bits

It compares the virtual address against every table entry until a matching physical frame is located

It hashes the whole virtual address into the page table to directly obtain the final physical address

It splits the address into a page number and offset, indexes the table for a frame, then adds the offset

It is the physical limit on how many transistors can be packed onto a single memory chip die

It is the growing gap between disk bandwidth and DRAM capacity, forcing frequent swapping to disk

It is the growing gap between fast CPU speeds and slower DRAM latency, forcing the CPU to stall

It is the point where adding more cache no longer improves the hit rate for any given workload

Aligned data uses less memory overall; unaligned access wastes cache space but runs at the same speed

Aligned data can be encrypted faster; unaligned access needs extra padding bytes added by the compiler

Aligned data avoids cache misses; unaligned access always causes a page fault that the OS must handle

Aligned data can be read in one access; unaligned access may need multiple accesses, slowing it down

SRAM and DRAM both use capacitors, but SRAM adds sense amplifiers that make cache lookups faster than main memory.

SRAM uses charge on capacitors that leaks away, while DRAM uses stable transistor latches that never require any refresh.

SRAM stores each bit in a capacitor cell, so it is dense; DRAM uses transistor flip-flops, so it is faster to read.

SRAM stores each bit in a transistor flip-flop, so it is fast; DRAM uses one transistor and a capacitor, so it is denser.

Unused bytes the compiler removes from members so the whole structure packs tightly into the fewest possible bytes.

Extra bytes the linker appends after each member so pointer arithmetic between structures always lands on a page boundary.

Extra bytes the CPU inserts at runtime near each member so misaligned accesses can be split across two machine words.

Unused bytes the compiler inserts between members so each starts at an address that is a multiple of its alignment.

DRAM cells lose charge to heat, so they must be periodically cooled; refresh uses power and permanently reduces overall bandwidth.

DRAM cells store bits as charge that leaks, so they must be periodically rewritten; refresh uses power and briefly stalls access.

DRAM transistors drift over time, so they must be periodically recalibrated; refresh uses power and slightly lowers the clock speed.

DRAM capacitors overcharge on writes, so they must be periodically drained; refresh uses power and doubles the effective access latency.

The CPU moves data with a faster instruction, so each word transfers to memory without waiting on the device to respond.

A controller moves data between two devices directly through cache, so the CPU can copy each word faster than via memory.

A controller moves data between device and memory directly, so the CPU is freed instead of copying each word itself.

A controller compresses data between device and memory during transfer, so the CPU handles fewer total words per block.

Polling wins when a device is fast and almost always ready, so interrupt overhead would exceed the cost of just checking.

Interrupts win when a device is fast and always ready, so polling overhead would exceed the cost of servicing each event.

Polling wins when many devices share one line, so the CPU can prioritize each interrupt instead of checking registers.

Polling wins when a device is slow and rarely ready, so the CPU avoids wasting cycles on frequent unnecessary interrupts.

MMIO maps device registers into the cache using normal load/store; a status flag tells the CPU each access targets a device.

MMIO uses a separate I/O address space with special IN/OUT instructions; the opcode tells the CPU each access targets a device.

PMIO maps device registers into the memory address space using normal load/store; a control line routes those ranges to devices.

MMIO maps device registers into the memory address space using normal load/store; address decoding routes those ranges to devices.

A trap is a synchronous intentional request, an exception is a synchronous error, and an interrupt is asynchronous from hardware

A trap and an interrupt are synchronous errors, while an exception is an intentional deliberate system call

All three are asynchronous events raised by external devices that request immediate CPU service handling

A trap is asynchronous from hardware, an exception is intentional, and an interrupt is a synchronous instruction fault

A mechanism that converts each device address into data so that memory can be read faster on the bus

A mechanism that encrypts bus traffic so that competing devices cannot read each other's transferred data blocks

A mechanism that decides which device gets control of the shared bus, preventing conflicts when several masters request it

A mechanism that widens the shared bus so every device can transmit at the exact same instant without waiting

The scheduler queues the interrupt with a priority and later dispatches its handler during a normal context switch

The handler address is permanently fixed in hardware, so all interrupts always run the same single routine directly

The CPU polls every attached device in sequence until it finds the one that actually raised the interrupt signal

The interrupt supplies an identifier used to index a vector table holding the handler address, so the CPU jumps to it

Threads are time-sliced by the operating system scheduler alone, so the hardware treats them just like two cores

Two logical threads each get a private cache and pipeline, giving the same throughput as two separate physical cores

One physical core runs multiple threads by fully duplicating its execution units, so it exactly equals two physical cores

One physical core runs multiple threads by sharing its execution units, whereas two physical cores duplicate all execution resources

SIMD runs independent instructions on independent data (multicore), while MIMD applies one instruction to many data elements (vector units)

SIMD and MIMD both apply one shared instruction stream, differing only in how many separate memory banks the cores can access

SIMD executes multiple instructions on a single data item, while MIMD executes a single instruction stream on one data item only

SIMD applies one instruction to many data elements (GPUs, vectors), while MIMD runs independent instructions on independent data (multicore)

SIMD processes one data item with many instructions per thread, unlike multithreading, and best suits sequential input-output work

SIMD runs one instruction across many data lanes in one thread, unlike multithreading's separate streams, aiding data-parallel tasks

SIMD and multithreading are identical mechanisms, both spawning threads, and both benefit unpredictable pointer-chasing workloads most

SIMD runs many independent instruction streams on separate cores, unlike multithreading, and mainly helps branch-heavy control tasks

In shared memory processors are limited to a single core each; in distributed memory processors can contain many independent cores per node.

In shared memory communication always uses a network switch; in distributed memory communication happens only through a shared system bus.

In shared memory all processors access one common address space; in distributed memory each has private memory and communicates by messages.

In shared memory each processor keeps private memory accessed by messages; in distributed memory all cores read one common global address space.

GPUs execute one thread at very high frequency per core, while CPUs split each instruction across many lanes for wide vector throughput.

GPUs rely on very large per-core caches to avoid stalls, while CPUs rely on massive thread counts to keep all execution units busy at once.

GPUs use thousands of simple cores running in SIMT fashion to hide latency, while CPUs use few complex cores tuned for low-latency serial work.

GPUs use a few high-clock cores optimized for branching, while CPUs use thousands of simple cores designed for streaming throughput tasks.

Both modes run the same instructions but rings merely change the virtual address space layout

User mode can run any instruction but rings block only direct memory writes into the kernel area

Kernel mode disables paging entirely while rings decide which cores may enter that mode at all

Kernel mode can run privileged instructions; protection rings restrict access by privilege level

Only the general-purpose registers are saved since the scheduler regenerates everything else later

The CPU registers, program counter, stack pointer, and status flags must be saved and restored

The program's heap, stack, and code segments are copied into a reserved kernel save area first

The entire cache and TLB contents must be flushed and copied into the process control block

Speedup is bounded by the parallel fraction, giving a maximum of about 90× overall

Speedup grows linearly with cores, so infinite cores give effectively unbounded speedup

Speedup equals the number of cores divided by ten, so it keeps rising with no fixed limit

Speedup is bounded by 1/(serial fraction), giving a maximum of 10×

The predictor stalls the pipeline until the condition resolves, and a flush is when cache lines holding the branch target are evicted to RAM

The predictor guesses the branch outcome to keep fetching; on a wrong guess the wrongly-fetched instructions are discarded in a flush

The predictor caches recent branch results in registers, and a flush is when the operating system forces a context switch mid-instruction

The predictor computes the branch target early using the ALU, and a flush occurs whenever two instructions need the same register at once

Immediate embeds a constant, register indirect uses a register as a pointer, and displacement adds an offset to a register, best for arrays

Immediate uses a register value, register indirect embeds a constant, and displacement dereferences a pointer twice, the last is ideal for arrays

Immediate reads from a fixed address, register indirect adds two registers, and displacement stores a pointer in memory, best used for arrays

Immediate points to the stack, register indirect adds a scaled index, and displacement holds an absolute address, displacement suits arrays best

Time = Instructions × cycle time ÷ CPI; performance improves whenever cycle time grows, because larger cycles do more work per step

Time = Instructions × CPI ÷ cycle time; performance improves whenever CPI drops, since a lower CPI always dominates the final result

Time = Instructions × CPI × cycle time; performance improves only if the CPI reduction outweighs the longer cycle time

Time = Instructions ÷ CPI × cycle time; performance improves only if instruction count also falls to offset the slower clock rate

PC-relative selects registers by numeric offset, aiding loops; indexed scales a constant by operand width, aiding struct fields.

PC-relative loads absolute targets stored near the code, aiding jumps; indexed reads pointers from a fixed table, aiding arrays.

PC-relative dereferences a pointer held in a register, aiding calls; indexed embeds the full target in the instruction, aiding data.

PC-relative adds an offset to the program counter, aiding branches; indexed adds a register to a base, aiding arrays.

They count raw operations without reflecting instruction complexity, ISA differences, or real workload behavior.

They rely on peak theoretical rates that programs rarely hit, plus they say nothing about work done per operation.

They only measure how fast the clock runs and ignore the memory hierarchy and pipeline stalls in the system.

They are computed differently by every vendor, so no two chips can ever be compared on the same numeric basis.

Clock is the bus rate, IPC is the memory latency; a lower clock outperforms when its instruction set is far simpler.

Clock is instructions per second, IPC is cycles per second; a slower clock wins by using shorter pipeline stages.

Clock counts cache hits, IPC counts branch predictions; lower clocks win because they generate far less heat overall.

Clock is cycles per second, IPC is instructions per cycle; higher IPC can beat a faster clock doing less.

RAID 0 mirrors for safety; RAID 1 stripes for speed; RAID 5 duplicates all data twice; RAID 10 uses dedicated parity disks.

RAID 0 stripes with no redundancy; RAID 1 mirrors; RAID 5 stripes with distributed parity; RAID 10 mirrors then stripes.

RAID 0 uses parity blocks; RAID 1 stripes across drives; RAID 5 mirrors every disk; RAID 10 stripes without any redundancy.

RAID 0 stores dual parity; RAID 1 stripes with checksums; RAID 5 mirrors pairs of disks; RAID 10 keeps a single hot spare.