Computer Architecture Junior

Memory capacity per dollar always halves every two years; this economic law still guides all chip design.

Transistor count on a chip roughly doubles every two years; scaling has slowed but remains relevant.

CPU clock speed roughly doubles every two years; this has fully held and continues without any slowdown.

Processor performance exactly doubles every eighteen months; it stopped being true right after year 2000.

General-purpose registers and the ALU/address paths are 64 bits wide, so integers and pointers are 64-bit.

The floating-point registers alone are 64 bits wide, so only double-precision math uses the full word size.

The instruction encodings are all 64 bits wide, so each machine instruction occupies a full 64-bit word.

The system memory bus and every cache line are 64 bits wide, so each fetch moves exactly 64 bits of data.

Instructions are hardwired into circuits while only data is kept in main memory.

Instructions and data share one memory, so code can be loaded and modified freely.

Each program keeps its instructions in a separate read-only memory from its data.

Programs run directly from external storage without ever loading into main memory.

It is the operating system layer that translates programs into signals for the hardware.

It describes the wiring of the memory bus so peripherals can communicate with the CPU.

It defines the instructions and registers software uses and hardware must implement.

It specifies the exact transistor layout that every compatible processor chip contains.

Moving from registers to disk, both capacity and speed increase while cost per byte rises.

Moving from registers to disk, capacity grows while speed rises and cost per byte rises.

Moving from registers to disk, capacity shrinks while speed rises and cost per byte falls.

Moving from registers to disk, capacity grows while speed and cost per byte both fall.

A word is the CPU's natural data unit, usually matching register, ALU, and bus width.

A word is always eight bits regardless of the register, ALU, or data-bus width used.

A word is the width of the address bus, which sets how much memory can be used.

A word is the smallest addressable memory cell, unrelated to register or bus width.

Register access, cache control, and interrupt handling routines.

Arithmetic/logic, data movement, and control flow operations.

Integer math, floating math, and vector processing operations.

Fetch, decode, and execute stages of the processor pipeline.

Big-endian stores the least significant byte first; endianness matters when allocating dynamic heap memory locally.

Big-endian stores the parity byte first; endianness matters when translating virtual addresses inside the CPU.

Big-endian stores the sign bit byte first; endianness matters when performing floating-point rounding in registers.

Big-endian stores the most significant byte first; endianness matters when exchanging binary data across systems.

Shift bits left by one for negatives; it gives one zero but needs separate subtract hardware.

Flip only the sign bit for negatives; it gives two zeros but unifies add/subtract hardware.

Add a bias constant for negatives; it gives two zeros and needs separate compare hardware.

Invert bits and add one for negatives; it gives one zero and unifies add/subtract hardware.

The extra high bits are placed in a separate register so the full wide result can still be recovered.

The result saturates at the maximum representable value and the carry flag is left unchanged.

The result wraps around modulo 2^n, and the overflow flag is set when the sign bit comes out wrong.

The CPU raises a hardware exception that halts the program before any incorrect value can be stored.

Two's complement uses a sign-magnitude form, whereas one's complement adds a fixed bias to shift the value range.

One's complement negates by inverting bits and adding one, while two's complement only inverts, yielding a single zero.

Two's complement negates by inverting bits and adding one, giving one zero; one's complement just inverts, giving two zeros.

Both invert all bits, but two's complement stores the sign in a separate flag and one's complement does not do that.

Latency is the queue length and throughput is the queue depth; reducing either just requires adding parallel execution units.

Latency is time per single task; throughput is tasks per unit time; batching or pipelining can raise one while hurting the other.

Latency measures memory bandwidth while throughput measures clock speed; tuning cache size trades one against the other.

Latency is tasks completed per unit time; throughput is the time per single task; the two always improve together in hardware.

Combinational circuits use a clock signal, while sequential circuits are purely asynchronous and hold no internal state.

Combinational output depends on stored state, while sequential output depends only on the present inputs at each moment.

Combinational circuits contain flip-flops for memory, whereas sequential circuits are built only from gates and wires.

Combinational output depends only on current inputs; sequential output also depends on stored state, so it has memory.

A circuit that adds several inputs into one output value, used to combine partial sums in the adder

A circuit that stores selected inputs across clock cycles, used to buffer operands entering the pipeline

A circuit that splits one input into several outputs by address, used to fan control signals through logic

A circuit that selects one of several inputs based on select lines, used to route sources into a datapath

A memory unit fetching operands from locations such as caches, registers, stacks, and buffers

A combinational unit performing arithmetic and logic operations such as add, subtract, AND, and OR

A sequential unit storing intermediate results such as flags, carries, operands, and pending writes

A control unit decoding instructions into signals such as reads, writes, jumps, and stalls

A stack of return values read through the top pointer and written through push logic during calls

An array of registers read through source ports and written through a destination port during execution

A block of cached memory read through the address bus and written through the data bus during fetch

A set of status flags read through the control unit and written through the ALU during decode

Fetch reads the instruction, Decode reads registers, Execute runs the ALU, Memory accesses data, Write-back stores the result.

Fetch reads registers, Decode runs the ALU, Execute reads the instruction, Memory writes back, Write-back accesses data memory.

Fetch runs the ALU, Decode accesses data memory, Execute reads registers, Memory writes back, Write-back reads instructions.

Fetch decodes the opcode, Decode accesses memory, Execute writes registers, Memory fetches data, Write-back runs the ALU.

Distant data is reused (temporal) and recent data is skipped (spatial), so caches prefetch only widely scattered addresses

Future data is predicted (temporal) and past data is dropped (spatial), so caches speculatively load unrelated memory pages

Recently used data is reused (temporal) and nearby data is used soon (spatial), so caches keep lines and fetch blocks

Random data is reused (temporal) and single bytes are used (spatial), so caches store one word per entry to save space

A single tagged word held per set; the 64 bytes are extra parity bits added to protect against memory bit errors

The smallest addressable unit in the cache; large lines exist mainly to match the CPU register width on each read

A page-sized region of memory; large lines let the TLB and cache share the same index bits to save silicon area

A fixed block transferred as a unit; larger lines exploit spatial locality and amortize tag and transfer overhead

ROM is fixed when made, PROM is written once, EPROM erases with UV light, EEPROM erases electrically per byte, flash erases in blocks.

ROM is fixed when made, PROM erases with UV light, EPROM is written once, EEPROM erases in blocks, flash erases electrically per byte.

ROM is written once by the user, PROM is fixed when made, EPROM erases in blocks, EEPROM erases with UV light, flash erases per byte.

ROM erases electrically, PROM erases with UV light, EPROM is written once, EEPROM is fixed when made, flash is programmed at the factory.

The address bus carries the data, the data bus selects locations, and the control bus stores the clock rate value

The address bus transfers data values, the data bus carries control signals, and the control bus holds the addresses

The address bus carries memory locations, the data bus transfers the actual data, and the control bus carries command and timing signals

The address bus and data bus both move data, while the control bus alone determines the processor clock frequency

SISD: many instructions, one data; SIMD: many instructions, many data; MISD: one instruction, one data; MIMD: one instruction, many data

SISD: one instruction, many data; SIMD: one instruction, one data; MISD: many instructions, many data; MIMD: many instructions, one data

SISD: one instruction, one data; SIMD: many instructions, one data; MISD: one instruction, many data; MIMD: many instructions, many data

SISD: one instruction, one data; SIMD: one instruction, many data; MISD: many instructions, one data; MIMD: many instructions, many data

A multicore has several cores on one physical chip, while a multiprocessor uses multiple separate CPU chips in different sockets.

A multicore runs one thread per core in turn, while a multiprocessor guarantees every thread runs simultaneously across all chips.

A multicore never shares cache across its cores, while a multiprocessor always shares one unified last-level cache between sockets.

A multicore places multiple chips into one socket, while a multiprocessor puts several cores onto a single shared processor die.

The PC holds the currently executing instruction, while the IR stores the address of the next instruction to be fetched from memory

The PC holds the address of the next instruction to fetch, while the IR holds the fetched instruction while it is decoded

The PC stores the decoded control signals, while the IR increments automatically to point at the following instruction in the sequence

The PC counts elapsed clock cycles, while the IR temporarily buffers operands read from registers before the ALU executes them

An HDD uses volatile memory cells refreshed constantly; an SSD uses optical disks read by lasers with slightly lower latency.

An HDD uses solid-state cells and needs no seek time; an SSD uses rotating platters and offers greater sequential speed.

An HDD uses spinning platters and moving heads with higher latency; an SSD uses flash with no moving parts and is faster.

An HDD uses flash chips with moving controllers and low latency; an SSD uses magnetic tape that is denser but far slower.

A parity bit sums all data bytes modulo 256; a checksum is a single bit appended to every transmitted data word.

A parity bit corrects flipped bits automatically; a checksum only signals that data was altered somewhere in transit.

A parity bit is one bit tracking odd/even count of 1s; a checksum is a wider sum catching more error patterns.

A parity bit encrypts the message before sending; a checksum verifies the sender's identity rather than the data.