Computer Architecture Expert

Memory capacity per dollar always halves every two years; this economic law still guides all chip design.

Transistor count on a chip roughly doubles every two years; scaling has slowed but remains relevant.

CPU clock speed roughly doubles every two years; this has fully held and continues without any slowdown.

Processor performance exactly doubles every eighteen months; it stopped being true right after year 2000.

General-purpose registers and the ALU/address paths are 64 bits wide, so integers and pointers are 64-bit.

The floating-point registers alone are 64 bits wide, so only double-precision math uses the full word size.

The instruction encodings are all 64 bits wide, so each machine instruction occupies a full 64-bit word.

The system memory bus and every cache line are 64 bits wide, so each fetch moves exactly 64 bits of data.

Instructions are hardwired into circuits while only data is kept in main memory.

Instructions and data share one memory, so code can be loaded and modified freely.

Each program keeps its instructions in a separate read-only memory from its data.

Programs run directly from external storage without ever loading into main memory.

It is the operating system layer that translates programs into signals for the hardware.

It describes the wiring of the memory bus so peripherals can communicate with the CPU.

It defines the instructions and registers software uses and hardware must implement.

It specifies the exact transistor layout that every compatible processor chip contains.

Moving from registers to disk, both capacity and speed increase while cost per byte rises.

Moving from registers to disk, capacity grows while speed rises and cost per byte rises.

Moving from registers to disk, capacity shrinks while speed rises and cost per byte falls.

Moving from registers to disk, capacity grows while speed and cost per byte both fall.

A word is the CPU's natural data unit, usually matching register, ALU, and bus width.

A word is always eight bits regardless of the register, ALU, or data-bus width used.

A word is the width of the address bus, which sets how much memory can be used.

A word is the smallest addressable memory cell, unrelated to register or bus width.

RISC always uses fewer registers; x86 adopted this to simplify its backward-compatible assembly.

RISC has more instructions overall; x86 chips now emulate them fully in a dedicated microcode ROM.

RISC uses simple fixed-length instructions; x86 decodes complex instructions into simpler internal micro-ops.

RISC runs at higher clock speeds; x86 shifted internally to reduce total transistor count and cost.

The mismatch between CPU and disk speeds stalls programs; caches and prefetching hide this latency fully.

The fixed instruction width wastes memory bandwidth badly; caches and prefetching compress the code stream.

The single shared path between CPU and memory limits throughput; caches and prefetching cut accesses.

The limited number of CPU registers forces spills to memory; caches and prefetching add register banks.

Harvard uses one memory for everything faster; Modified Harvard adds a second slower memory for backups.

Von Neumann needs two clocks per access always; Modified Harvard runs both instruction fetches in parallel.

Von Neumann shares one memory for code and data; Modified Harvard splits caches but shares main memory.

Von Neumann splits code and data buses; Modified Harvard merges them to reduce total pin count needs.

ISA is the physical chip layout; microarchitecture is the abstract model, so the same code runs slowly.

ISA is the instruction contract; microarchitecture is how it's built, so implementations differ in speed.

ISA defines clock frequency limits; microarchitecture defines the software, so performance varies by compiler.

ISA is the operating system layer; microarchitecture is the transistor process, so newer nodes run faster.

64-bit ISAs guarantee out-of-order execution support, mainly improving branch prediction accuracy overall.

64-bit ISAs expose more and wider registers, easing register pressure and enabling larger operations.

64-bit ISAs double the clock rate and cache size, mainly cutting the number of pipeline stall cycles.

64-bit ISAs add fixed-length instructions and remove microcode, mainly simplifying the instruction decoder.

CISC favors simple uniform instructions and lower power, so it dominates the small mobile device market.

RISC favors complex multi-step instructions and compatibility, so servers keep choosing it for raw speed.

RISC favors variable-length dense encoding and legacy support, giving it a clear edge in energy per task.

RISC favors simple uniform instructions and power efficiency, winning in mobile and now dense servers.

Register access, cache control, and interrupt handling routines.

Arithmetic/logic, data movement, and control flow operations.

Integer math, floating math, and vector processing operations.

Fetch, decode, and execute stages of the processor pipeline.

Every arithmetic instruction reads and writes memory without using any registers at all.

Arithmetic instructions may read memory operands directly but cannot write to memory.

Only load and store instructions touch memory; arithmetic works purely on registers.

Loads and stores are combined with arithmetic into single instructions for operands.

Stack machines address operands explicitly; modern CPUs use them for simpler compact code.

Stack machines keep operands in named registers; modern CPUs prefer them for easy decoding.

Register machines push operands onto a stack; modern CPUs avoid them due to complexity.

Register machines address operands explicitly; modern CPUs use them for speed and reordering.

Opcode names the operation, operand fields name the data; encoding sets code density and decode speed.

Opcode names the register, operand fields name the address; encoding sets cache hit rates and latency.

Opcode names the pipeline stage, operand fields name the ports; encoding sets clock frequency and power.

Opcode names the data type, operand fields name the offsets; encoding sets branch prediction accuracy.

The stack saves return addresses and registers; a calling convention defines argument and register rules.

The stack saves cache lines and page tables; a calling convention defines interrupt and priority rules.

The stack saves opcode fields and flags; a calling convention defines memory alignment and paging rules.

The stack saves branch targets and counters; a calling convention defines pipeline and hazard rules.

Both fixed and variable length decode identically, differing only in the memory they use.

Fixed length improves code density while variable length is simpler and faster to decode.

Variable length eases pipelining while fixed length always yields the most compact code.

Fixed length eases decoding but wastes space; variable length packs code but decodes slower.

Microcode breaks complex instructions into simple micro-ops the core executes efficiently.

Microcode is firmware on disk that boots the processor before any instructions can run.

Microcode is a cache layer that stores decoded instructions to skip fetching them again.

Microcode is the compiler pass that converts source code into machine instructions for x86.

VLIW schedules parallel operations in hardware, while superscalar finds parallelism in the compiler.

VLIW executes one operation per cycle strictly, while superscalar runs several threads concurrently.

VLIW reorders memory accesses dynamically, while superscalar issues instructions strictly in order.

VLIW schedules parallel operations in the compiler, while superscalar finds parallelism in hardware.

Big-endian stores the least significant byte first; endianness matters when allocating dynamic heap memory locally.

Big-endian stores the parity byte first; endianness matters when translating virtual addresses inside the CPU.

Big-endian stores the sign bit byte first; endianness matters when performing floating-point rounding in registers.

Big-endian stores the most significant byte first; endianness matters when exchanging binary data across systems.

Shift bits left by one for negatives; it gives one zero but needs separate subtract hardware.

Flip only the sign bit for negatives; it gives two zeros but unifies add/subtract hardware.

Add a bias constant for negatives; it gives two zeros and needs separate compare hardware.

Invert bits and add one for negatives; it gives one zero and unifies add/subtract hardware.

The extra high bits are placed in a separate register so the full wide result can still be recovered.

The result saturates at the maximum representable value and the carry flag is left unchanged.

The result wraps around modulo 2^n, and the overflow flag is set when the sign bit comes out wrong.

The CPU raises a hardware exception that halts the program before any incorrect value can be stored.

Two's complement uses a sign-magnitude form, whereas one's complement adds a fixed bias to shift the value range.

One's complement negates by inverting bits and adding one, while two's complement only inverts, yielding a single zero.

Two's complement negates by inverting bits and adding one, giving one zero; one's complement just inverts, giving two zeros.

Both invert all bits, but two's complement stores the sign in a separate flag and one's complement does not do that.

They round toward zero by default, so bias occurs; IEEE-754 stores flag, magnitude, and length fields.

They lack an exact binary form, so rounding occurs; IEEE-754 stores sign, exponent, and mantissa.

They exceed the register width limit, so truncation occurs; IEEE-754 stores base, offset, and remainder.

They use decimal not binary encoding, so overflow occurs; IEEE-754 stores digit, scale, and precision.

Signed values reserve an extra bit outside the word, so they occupy a wider register than unsigned values do.

The ALU tags every value with a type at load time, and each unit reads that tag before it operates on it.

A dedicated sign flag inside each register marks whether the value stored there should be treated as signed.

The bits are identical; the chosen instructions (signed vs unsigned compares, sign vs zero extension) fix the interpretation.

NaN is max exponent with zero mantissa; infinity is max exponent with nonzero mantissa; subnormals use a max exponent field throughout.

Infinity is zero exponent with max mantissa; NaN is zero exponent with zero mantissa; subnormals are encoded using only the sign bit.

Subnormals are max exponent with zero mantissa; infinity uses a zero exponent; NaN is any value whose sign bit has been set to one.

Infinity is max exponent with zero mantissa; NaN is max exponent with nonzero mantissa; subnormals are zero exponent with nonzero mantissa.

The exponent is stored in two's complement, and the bias corrects the sign so the hardware can add exponents faster.

A fixed constant is added to the exponent so it is stored unsigned, letting plain integer comparison order floats correctly.

A fixed constant is subtracted from the mantissa so that very small numbers can be encoded without losing precision bits.

A scaling factor multiplies the exponent so that one shared encoding can cover both single and double precision formats.

Use fixed-point for wider dynamic range and cheaper storage, trading away deterministic rounding behavior.

Use fixed-point for larger exponent handling and speed, trading away compact operand encoding widths.

Use fixed-point for automatic scaling and higher accuracy, trading away simpler integer arithmetic units.

Use fixed-point for deterministic precision and simpler, faster arithmetic, trading away dynamic range.

Nearest (ties to even), toward zero, toward +∞, and toward −∞; the mode controls how much error accumulates.

Nearest, floor, ceiling, and modulo rounding; the mode mainly affects arithmetic speed rather than accuracy.

Truncate, round half up, round half down, and random rounding; choosing a mode forces the total error to zero.

Banker's, statistical, exact, and lossless rounding; picking one guarantees results identical to real arithmetic.

Latency is the queue length and throughput is the queue depth; reducing either just requires adding parallel execution units.

Latency is time per single task; throughput is tasks per unit time; batching or pipelining can raise one while hurting the other.

Latency measures memory bandwidth while throughput measures clock speed; tuning cache size trades one against the other.

Latency is tasks completed per unit time; throughput is the time per single task; the two always improve together in hardware.

Combinational circuits use a clock signal, while sequential circuits are purely asynchronous and hold no internal state.

Combinational output depends on stored state, while sequential output depends only on the present inputs at each moment.

Combinational circuits contain flip-flops for memory, whereas sequential circuits are built only from gates and wires.

Combinational output depends only on current inputs; sequential output also depends on stored state, so it has memory.

A circuit that adds several inputs into one output value, used to combine partial sums in the adder

A circuit that stores selected inputs across clock cycles, used to buffer operands entering the pipeline

A circuit that splits one input into several outputs by address, used to fan control signals through logic

A circuit that selects one of several inputs based on select lines, used to route sources into a datapath

A memory unit fetching operands from locations such as caches, registers, stacks, and buffers

A combinational unit performing arithmetic and logic operations such as add, subtract, AND, and OR

A sequential unit storing intermediate results such as flags, carries, operands, and pending writes

A control unit decoding instructions into signals such as reads, writes, jumps, and stalls

A stack of return values read through the top pointer and written through push logic during calls

An array of registers read through source ports and written through a destination port during execution

A block of cached memory read through the address bus and written through the data bus during fetch

A set of status flags read through the control unit and written through the ALU during decode

A latch is level-sensitive while a flip-flop is edge-triggered, so flip-flops sample data at defined clock edges

A latch is asynchronous while a flip-flop is combinational, so flip-flops react faster to input changes

A latch is edge-triggered while a flip-flop is level-sensitive, so flip-flops hold data during clock pulses

A latch stores multiple bits while a flip-flop stores one bit, so flip-flops save area in register files

The time a register needs to reset its state; the total gate count sets the achievable clock period

The time a signal stays stable at a gate; the shortest such path sets the maximum clock period

The time between two consecutive clock edges; the average path length sets the usable clock period

The time for a signal to travel through logic; the longest such path sets the minimum clock period

It synchronizes state updates across elements; skew is the difference in clock arrival times between them

It selects which instruction executes next in order; skew is the delay added by a mispredicted branch path

It counts the cycles used by each executed instruction; skew is the gap between issued and retired counts

It supplies operating power to the logic elements; skew is the variation in voltage delivered to each one

Hardwired executes only reduced instructions directly; microprogrammed executes only complex ones in software

Hardwired decodes instructions during compilation; microprogrammed decodes them entirely at runtime instead

Hardwired generates control signals with fixed logic gates; microprogrammed reads them from control memory

Hardwired reads control signals from stored memory; microprogrammed generates them with fixed logic gates

Single-cycle overlaps several instructions per cycle; multi-cycle issues only one instruction across many cycles

Single-cycle runs each instruction in one long cycle; multi-cycle splits work into shorter cycles reusing units

Single-cycle uses microcode for each cycle step; multi-cycle uses hardwired logic to finish in one fixed cycle

Single-cycle splits work into shorter cycles reusing units; multi-cycle runs each instruction in one long cycle

Fetch reads the instruction, Decode reads registers, Execute runs the ALU, Memory accesses data, Write-back stores the result.

Fetch reads registers, Decode runs the ALU, Execute reads the instruction, Memory writes back, Write-back accesses data memory.

Fetch runs the ALU, Decode accesses data memory, Execute reads registers, Memory writes back, Write-back reads instructions.

Fetch decodes the opcode, Decode accesses memory, Execute writes registers, Memory fetches data, Write-back runs the ALU.

Data, control, and cache hazards; forwarding flushes the pipeline and refetches the stalled dependent instruction from main memory.

Structural, logical, and input/output hazards; forwarding duplicates the register file so two stages can read one value.

Timing, memory, and branch hazards; forwarding delays the dependent instruction until the register file has finally been updated.

Structural, data, and control hazards; forwarding routes an execution result directly to a later instruction's input before write-back.

Running independent instructions on separate cores in parallel raises throughput while the single-core latency of each instruction is unchanged.

Caching recently used results lets instructions skip stages, which increases throughput and simultaneously lowers each instruction's latency.

Overlapping stages of multiple instructions raises completed-instructions-per-cycle while each instruction's own end-to-end latency stays roughly the same.

Executing each instruction faster shortens its latency, and the faster instructions naturally raise the overall throughput of the pipeline.

It renames the destination register so the reader and writer no longer share a name and can run in either order.

It stalls the dependent instruction for several cycles until the produced value is safely committed into the register file.

It reorders the two instructions so the reading instruction executes fully before the writing instruction ever enters the pipeline.

It routes a result from a later pipeline stage straight to a dependent instruction's input, avoiding the wait for write-back.

Per-instruction latency usually rises slightly while throughput improves thanks to a higher achievable clock frequency.

Latency stays fixed while throughput falls because deeper pipelines suffer many more structural resource hazards.

Per-instruction latency falls sharply while throughput drops because each stage now performs far less useful work.

Both latency and throughput improve equally since more stages mean more instructions finish in every clock cycle.

A bubble is a mispredicted branch that flushes the pipeline; stalling avoids all penalties while prediction guarantees maximum throughput.

A bubble is an injected no-op that stalls flow; stalling wastes cycles reliably while prediction risks a costly flush when it is wrong.

A bubble is an extra execution stage added for hazards; stalling raises the clock rate while prediction lowers it and adds complexity.

A bubble is a cache miss that halts fetch; stalling always beats prediction because prediction can never recover the lost cycles at all.

A superscalar issues multiple instructions per cycle via duplicated units, while a simple pipeline issues one per cycle

A superscalar always executes strictly in order, while a simple pipeline reorders instructions to fill more slots per cycle

A superscalar runs at a much higher clock rate, while a simple pipeline compensates by widening its data path per cycle

A superscalar removes the pipeline stages entirely, while a simple pipeline overlaps stages of one instruction per cycle

The ROB schedules ready instructions to execution units out of order and lets each one commit immediately as soon as it finishes.

The ROB holds finished instructions in program order and commits their results in that order even though they executed out of order.

The ROB stores branch predictions in order and discards them once the correct execution path through the program has been resolved.

The ROB caches memory operands in program order so that load and store instructions can bypass the slower data cache entirely.

It maps architectural registers onto a larger physical set, so name-reuse WAR/WAW dependencies vanish and more instructions run in parallel.

It reorders instructions that share a register name at compile time, so the WAR/WAW pairs never appear together inside the pipeline.

It stalls instructions that reuse a register name until the prior writer commits, so the WAR/WAW ordering is preserved and made safe.

It forwards each result directly between stages, so the reused register name is never read early and every WAR/WAW hazard is bypassed.

Out-of-order skips stalled instructions permanently, using a write buffer to discard results that arrive later than expected

Out-of-order fetches instructions backwards from memory, using a branch predictor to reorder the whole instruction stream

Out-of-order runs ready instructions early despite program order, using a reorder buffer to retire results in order

Out-of-order runs instructions on multiple cores at once, using a shared cache to keep every result globally consistent

It hides latency by executing independent work early, while in-order retirement commits results and exceptions in program order

It saves power by pausing idle units early, while the memory controller replays each store to restore its correct ordering

It boosts throughput by duplicating registers early, while the compiler inserts barriers that force results back into order

It raises clock speed by shortening pipeline stages, while a checksum unit verifies that outputs match the original ordering

The compiler statically orders instructions so hardware never needs to stall waiting on any pending operand values

Reservation stations track operands and register renaming removes false dependencies so instructions issue when ready

A lookahead unit precomputes all branch targets so dependent instructions can be dispatched together far ahead of time

A central queue forces every instruction to wait for the previous one to fully commit before its operands are read

Distant data is reused (temporal) and recent data is skipped (spatial), so caches prefetch only widely scattered addresses

Future data is predicted (temporal) and past data is dropped (spatial), so caches speculatively load unrelated memory pages

Recently used data is reused (temporal) and nearby data is used soon (spatial), so caches keep lines and fetch blocks

Random data is reused (temporal) and single bytes are used (spatial), so caches store one word per entry to save space

A single tagged word held per set; the 64 bytes are extra parity bits added to protect against memory bit errors

The smallest addressable unit in the cache; large lines exist mainly to match the CPU register width on each read

A page-sized region of memory; large lines let the TLB and cache share the same index bits to save silicon area

A fixed block transferred as a unit; larger lines exploit spatial locality and amortize tag and transfer overhead

Write-through skips the cache completely; write-back stores data twice to guarantee memory always stays consistent

Write-through updates memory on every write; write-back defers writes until eviction, reducing memory traffic

Write-through updates only the cache line; write-back copies the entire cache to memory on every single store

Write-through buffers writes until a flush; write-back writes to memory immediately for maximum data durability

Direct-mapped has slow hits but few misses; fully-associative raises misses but is faster; set-associative worsens both

Direct-mapped has fast hits but more misses; fully-associative lowers misses but is slower; set-associative balances both

Direct-mapped has slow hits and many misses; fully-associative fixes both; set-associative offers no real advantage at all

Direct-mapped has fast hits and few misses; fully-associative also has fast hits; set-associative is slower on every access

Compulsory misses occur on first access to a block; increasing associativity fully eliminates them from the cache

Capacity misses occur when the working set fits; shrinking the block size lets more distinct lines coexist in it

Conflict misses occur from a cold cache at startup; prefetching every block ahead of time removes each of them

Conflict misses occur when too many blocks map to one set; adjusting data layout or padding spreads accesses out

AMAT = hit time + miss rate × miss penalty, where each level's miss penalty is the AMAT of the next lower level

AMAT = miss rate × (hit time + miss penalty), computed independently per level and then averaged across every level

AMAT = hit time + miss penalty − miss rate, where the miss penalty stays fixed as the main memory latency throughout

AMAT = hit time × miss rate + miss penalty, summed once over all levels using only the last level's global miss rate

True LRU is trivial in hardware since only one counter per cache is needed, so it is always chosen over random

FIFO always outperforms LRU on real workloads, so true LRU is avoided purely because of its worse hit rates

True LRU must track full recency order per set, costing bits and logic, so hardware uses cheaper approximations

Random needs the most storage of the three, so designers pick true LRU to save area despite the timing penalty

Write-allocate applies only to read misses; no-write-allocate applies only to write hits within a write-back cache line

Write-allocate flushes the whole set on a miss; no-write-allocate keeps the set intact and stalls the pipeline instead

Write-allocate loads the block into the cache on a miss; no-write-allocate writes straight to memory without loading

Write-allocate writes only to memory on a miss; no-write-allocate loads the block first then updates it in the cache

A unified cache holds only data, and L1 splits so instructions can bypass coherence traffic between the core caches

A split cache keeps instructions and data separate, letting fetch and load happen at once without structural hazards

A split cache uses one large port shared by both, and L1 splits so the tag array can be indexed with fewer bits

A split cache stores both streams together, and L1 splits it mainly to double the total capacity of the fast cache

The offset selects the set to probe, the index identifies the block, and the tag selects a byte inside that one block

The tag selects a byte within a block, the offset selects the set, and the index identifies the block within that set

The index selects a byte within a block, the tag selects the set, and the offset identifies the block within that set

The offset selects a byte within a block, the index selects the set, and the tag identifies the block within that set

They compress cache lines on the fly; hardware prefetchers detect duplicate blocks so more data fits near the core

They evict stale data ahead of time; hardware prefetchers scan the tag array to free sets before a miss can occur

They reorder memory writes for locality; hardware prefetchers batch stores together to reduce total bus transactions

They fetch data before it is requested; hardware prefetchers detect access patterns to overlap fetches with compute

Inclusive stores each line in only a single level; exclusive duplicates every line across all levels to speed up coherence

Inclusive allows only read data to be cached; exclusive allows only writes, splitting the hierarchy strictly by access type

Inclusive keeps lower-level data duplicated in higher levels; exclusive holds each line in only one level to save capacity

Inclusive bypasses the last-level cache entirely; exclusive routes all data through it to keep every level fully synchronized

It caches recent memory blocks; a miss triggers a page-table walk, while a page fault means the page is not in RAM

It caches address translations; a miss means the page is not in RAM, while a page fault triggers a page-table walk

It buffers pending writes; a miss stalls the CPU, while a page fault evicts a line from the L2 cache entirely

It caches address translations; a miss triggers a page-table walk, while a page fault means the page is not in RAM

The TLB fetches the missing page from disk automatically without any operating-system involvement

The MMU raises a trap, and the OS handler loads the page from disk and updates the page table

The MMU flushes the TLB, evicts a cache line, and the branch predictor reroutes the pipeline flow

The CPU invalidates its caches and keeps retrying the instruction until the page appears in memory

It splits the address into a tag and index, looks up the cache, then appends the remaining offset bits

It compares the virtual address against every table entry until a matching physical frame is located

It hashes the whole virtual address into the page table to directly obtain the final physical address

It splits the address into a page number and offset, indexes the table for a frame, then adds the offset

The TLB sits after the L1 cache, so both VIPT and PIPT tag the cache with virtual addresses

VIPT waits for the TLB to finish translating before it can index and compare the cache tags

PIPT indexes with virtual bits while the TLB translates in parallel, then compares virtual tags

VIPT indexes with virtual bits while the TLB translates in parallel, then compares physical tags

It walks the multi-level page table, using address bits to index each level down to the final frame

It searches the L2 cache for the translation, using address bits to locate the matching frame entry

It walks the multi-level page table, storing every possible entry so no memory is ever left unused

It interrupts the OS, which linearly scans a single flat table to find the correct frame number

Both translate the address first, but VIPT is faster because it stores larger cache line blocks

PIPT overlaps cache indexing with TLB translation, while VIPT must translate before it can index

VIPT overlaps cache indexing with TLB translation, while PIPT must translate before it can index

VIPT and PIPT both index after translation; the difference is only in how the tags are stored

ROM is fixed when made, PROM is written once, EPROM erases with UV light, EEPROM erases electrically per byte, flash erases in blocks.

ROM is fixed when made, PROM erases with UV light, EPROM is written once, EEPROM erases in blocks, flash erases electrically per byte.

ROM is written once by the user, PROM is fixed when made, EPROM erases in blocks, EEPROM erases with UV light, flash erases per byte.

ROM erases electrically, PROM erases with UV light, EPROM is written once, EEPROM is fixed when made, flash is programmed at the factory.

It is the physical limit on how many transistors can be packed onto a single memory chip die

It is the growing gap between disk bandwidth and DRAM capacity, forcing frequent swapping to disk

It is the growing gap between fast CPU speeds and slower DRAM latency, forcing the CPU to stall

It is the point where adding more cache no longer improves the hit rate for any given workload

Aligned data uses less memory overall; unaligned access wastes cache space but runs at the same speed

Aligned data can be encrypted faster; unaligned access needs extra padding bytes added by the compiler

Aligned data avoids cache misses; unaligned access always causes a page fault that the OS must handle

Aligned data can be read in one access; unaligned access may need multiple accesses, slowing it down

SRAM and DRAM both use capacitors, but SRAM adds sense amplifiers that make cache lookups faster than main memory.

SRAM uses charge on capacitors that leaks away, while DRAM uses stable transistor latches that never require any refresh.

SRAM stores each bit in a capacitor cell, so it is dense; DRAM uses transistor flip-flops, so it is faster to read.

SRAM stores each bit in a transistor flip-flop, so it is fast; DRAM uses one transistor and a capacitor, so it is denser.

Unused bytes the compiler removes from members so the whole structure packs tightly into the fewest possible bytes.

Extra bytes the linker appends after each member so pointer arithmetic between structures always lands on a page boundary.

Extra bytes the CPU inserts at runtime near each member so misaligned accesses can be split across two machine words.

Unused bytes the compiler inserts between members so each starts at an address that is a multiple of its alignment.

DRAM cells lose charge to heat, so they must be periodically cooled; refresh uses power and permanently reduces overall bandwidth.

DRAM cells store bits as charge that leaks, so they must be periodically rewritten; refresh uses power and briefly stalls access.

DRAM transistors drift over time, so they must be periodically recalibrated; refresh uses power and slightly lowers the clock speed.

DRAM capacitors overcharge on writes, so they must be periodically drained; refresh uses power and doubles the effective access latency.

Consecutive addresses are compressed before storage across banks and channels so more data fits, increasing the usable bandwidth.

Consecutive addresses are duplicated across multiple banks and channels so failed reads can retry elsewhere, improving reliability.

Consecutive addresses are grouped into one bank and channel so accesses stay local, reducing latency but limiting total bandwidth.

Consecutive addresses are spread across multiple banks and channels so accesses overlap in parallel, raising effective bandwidth.

The address bus carries the data, the data bus selects locations, and the control bus stores the clock rate value

The address bus transfers data values, the data bus carries control signals, and the control bus holds the addresses

The address bus carries memory locations, the data bus transfers the actual data, and the control bus carries command and timing signals

The address bus and data bus both move data, while the control bus alone determines the processor clock frequency

The CPU moves data with a faster instruction, so each word transfers to memory without waiting on the device to respond.

A controller moves data between two devices directly through cache, so the CPU can copy each word faster than via memory.

A controller moves data between device and memory directly, so the CPU is freed instead of copying each word itself.

A controller compresses data between device and memory during transfer, so the CPU handles fewer total words per block.

Polling wins when a device is fast and almost always ready, so interrupt overhead would exceed the cost of just checking.

Interrupts win when a device is fast and always ready, so polling overhead would exceed the cost of servicing each event.

Polling wins when many devices share one line, so the CPU can prioritize each interrupt instead of checking registers.

Polling wins when a device is slow and rarely ready, so the CPU avoids wasting cycles on frequent unnecessary interrupts.

MMIO maps device registers into the cache using normal load/store; a status flag tells the CPU each access targets a device.

MMIO uses a separate I/O address space with special IN/OUT instructions; the opcode tells the CPU each access targets a device.

PMIO maps device registers into the memory address space using normal load/store; a control line routes those ranges to devices.

MMIO maps device registers into the memory address space using normal load/store; address decoding routes those ranges to devices.

A trap is a synchronous intentional request, an exception is a synchronous error, and an interrupt is asynchronous from hardware

A trap and an interrupt are synchronous errors, while an exception is an intentional deliberate system call

All three are asynchronous events raised by external devices that request immediate CPU service handling

A trap is asynchronous from hardware, an exception is intentional, and an interrupt is a synchronous instruction fault

A mechanism that converts each device address into data so that memory can be read faster on the bus

A mechanism that encrypts bus traffic so that competing devices cannot read each other's transferred data blocks

A mechanism that decides which device gets control of the shared bus, preventing conflicts when several masters request it

A mechanism that widens the shared bus so every device can transmit at the exact same instant without waiting

The scheduler queues the interrupt with a priority and later dispatches its handler during a normal context switch

The handler address is permanently fixed in hardware, so all interrupts always run the same single routine directly

The CPU polls every attached device in sequence until it finds the one that actually raised the interrupt signal

The interrupt supplies an identifier used to index a vector table holding the handler address, so the CPU jumps to it

SISD: many instructions, one data; SIMD: many instructions, many data; MISD: one instruction, one data; MIMD: one instruction, many data

SISD: one instruction, many data; SIMD: one instruction, one data; MISD: many instructions, many data; MIMD: many instructions, one data

SISD: one instruction, one data; SIMD: many instructions, one data; MISD: one instruction, many data; MIMD: many instructions, many data

SISD: one instruction, one data; SIMD: one instruction, many data; MISD: many instructions, one data; MIMD: many instructions, many data

A multicore has several cores on one physical chip, while a multiprocessor uses multiple separate CPU chips in different sockets.

A multicore runs one thread per core in turn, while a multiprocessor guarantees every thread runs simultaneously across all chips.

A multicore never shares cache across its cores, while a multiprocessor always shares one unified last-level cache between sockets.

A multicore places multiple chips into one socket, while a multiprocessor puts several cores onto a single shared processor die.

Threads are time-sliced by the operating system scheduler alone, so the hardware treats them just like two cores

Two logical threads each get a private cache and pipeline, giving the same throughput as two separate physical cores

One physical core runs multiple threads by fully duplicating its execution units, so it exactly equals two physical cores

One physical core runs multiple threads by sharing its execution units, whereas two physical cores duplicate all execution resources

SIMD runs independent instructions on independent data (multicore), while MIMD applies one instruction to many data elements (vector units)

SIMD and MIMD both apply one shared instruction stream, differing only in how many separate memory banks the cores can access

SIMD executes multiple instructions on a single data item, while MIMD executes a single instruction stream on one data item only

SIMD applies one instruction to many data elements (GPUs, vectors), while MIMD runs independent instructions on independent data (multicore)

SIMD processes one data item with many instructions per thread, unlike multithreading, and best suits sequential input-output work

SIMD runs one instruction across many data lanes in one thread, unlike multithreading's separate streams, aiding data-parallel tasks

SIMD and multithreading are identical mechanisms, both spawning threads, and both benefit unpredictable pointer-chasing workloads most

SIMD runs many independent instruction streams on separate cores, unlike multithreading, and mainly helps branch-heavy control tasks

In shared memory processors are limited to a single core each; in distributed memory processors can contain many independent cores per node.

In shared memory communication always uses a network switch; in distributed memory communication happens only through a shared system bus.

In shared memory all processors access one common address space; in distributed memory each has private memory and communicates by messages.

In shared memory each processor keeps private memory accessed by messages; in distributed memory all cores read one common global address space.

GPUs execute one thread at very high frequency per core, while CPUs split each instruction across many lanes for wide vector throughput.

GPUs rely on very large per-core caches to avoid stalls, while CPUs rely on massive thread counts to keep all execution units busy at once.

GPUs use thousands of simple cores running in SIMT fashion to hide latency, while CPUs use few complex cores tuned for low-latency serial work.

GPUs use a few high-clock cores optimized for branching, while CPUs use thousands of simple cores designed for streaming throughput tasks.

UMA scales better for large servers because remote access is free, while NUMA forces every access to go through one shared controller

UMA and NUMA both provide uniform latency, but NUMA simply adds more channels, so data placement never affects performance at all

UMA gives each processor its own local memory bank, while NUMA shares one uniform memory pool with equal latency for all cores

UMA gives all processors uniform memory latency, while NUMA has faster local memory, so software should keep data near the accessing CPU

MESI marks each line Managed, Exclusive, Stored, or Idle so multiple cores can freely write the same line while hardware merges the written results.

MESI copies every write immediately to all caches at once so every core keeps an identical full duplicate of the shared main memory contents.

MESI locks the entire cache during any write so that no other core can read memory until the writing core has fully flushed its pending changes.

MESI marks each line Modified, Exclusive, Shared, or Invalid so only one core writes a line and others always observe consistent, non-stale data.

Independent variables placed on the same cache line cause cross-core invalidations on writes; align or pad data to separate lines to prevent it.

Two cores read the same shared variable and stall on its lock; assign each core its own private copy of the variable to remove the contention.

A cache line is evicted too early because of limited capacity; increase the cache associativity so that hot lines are retained longer for reuse.

One core writes memory another has cached as valid data; disable the cache entirely on that region so all accesses go straight to main RAM.

It pauses all other cores until the current core completes, ensuring that only one memory operation is ever in flight at any given moment.

It enforces an ordering constraint on memory operations, stopping hardware or compiler from reordering loads and stores across the barrier.

It flushes the entire cache hierarchy back to main memory, guaranteeing every core immediately sees a fully coherent global view of memory.

It converts weakly-ordered accesses into atomic transactions, so that grouped reads and writes always commit together as one indivisible unit.

Snooping stores data only in main memory and suits small systems; directory-based caches everything locally and suits very large-scale systems.

Snooping keeps a central table of all sharers and suits large systems; directory-based broadcasts on a shared bus and suits only smaller systems.

Snooping broadcasts coherence traffic on a shared bus and suits small systems; directory-based tracks sharers in a directory and scales larger.

Snooping requires software to manage coherence and suits small systems; directory-based lets hardware manage it and suits many-core systems best.

Owned forces an immediate writeback to memory whenever any core reads that shared cache line

Owned lets one cache hold dirty data and supply it to others without writing back to memory

Owned marks a line as exclusive and clean so writes proceed with no bus transaction at all

Owned allows two separate caches to both write the same line at once via a locked bus cycle

CAS spins in software rereading a value until two consecutive reads return identical results

CAS disables all interrupts while it reads then writes a value, so no other core can interfere

CAS locks the whole cache line permanently until the owning thread explicitly releases it

CAS atomically compares a location to an expected value and updates it only if they match

Sequential consistency permits any reordering while relaxed models strictly forbid all reordering

Sequential consistency preserves program order globally; relaxed models let loads and stores reorder

Sequential consistency requires atomics whereas relaxed ordering by itself guarantees cache coherence

Sequential consistency applies only to caches while relaxed models apply only to main memory access

Both modes run the same instructions but rings merely change the virtual address space layout

User mode can run any instruction but rings block only direct memory writes into the kernel area

Kernel mode disables paging entirely while rings decide which cores may enter that mode at all

Kernel mode can run privileged instructions; protection rings restrict access by privilege level

Only the general-purpose registers are saved since the scheduler regenerates everything else later

The CPU registers, program counter, stack pointer, and status flags must be saved and restored

The program's heap, stack, and code segments are copied into a reserved kernel save area first

The entire cache and TLB contents must be flushed and copied into the process control block

They encrypt all guest memory pages transparently to isolate virtual machines from one another

They emulate privileged instructions in microcode so the hypervisor never has to intervene at all

They provide extra general-purpose registers dedicated to storing each guest operating system

They add a new CPU execution mode that traps privileged guest instructions to the hypervisor

It assigns interrupt priorities to devices so passthrough guests receive their events in fair order

It remaps and restricts device DMA addresses, isolating devices and enabling safe passthrough

It translates virtual addresses for the CPU cores while devices access physical memory directly

It caches device I/O requests in a buffer to speed up repeated DMA transfers into memory

The PC holds the currently executing instruction, while the IR stores the address of the next instruction to be fetched from memory

The PC holds the address of the next instruction to fetch, while the IR holds the fetched instruction while it is decoded

The PC stores the decoded control signals, while the IR increments automatically to point at the following instruction in the sequence

The PC counts elapsed clock cycles, while the IR temporarily buffers operands read from registers before the ALU executes them

An HDD uses volatile memory cells refreshed constantly; an SSD uses optical disks read by lasers with slightly lower latency.

An HDD uses solid-state cells and needs no seek time; an SSD uses rotating platters and offers greater sequential speed.

An HDD uses spinning platters and moving heads with higher latency; an SSD uses flash with no moving parts and is faster.

An HDD uses flash chips with moving controllers and low latency; an SSD uses magnetic tape that is denser but far slower.

A parity bit sums all data bytes modulo 256; a checksum is a single bit appended to every transmitted data word.

A parity bit corrects flipped bits automatically; a checksum only signals that data was altered somewhere in transit.

A parity bit is one bit tracking odd/even count of 1s; a checksum is a wider sum catching more error patterns.

A parity bit encrypts the message before sending; a checksum verifies the sender's identity rather than the data.

Speedup is bounded by the parallel fraction, giving a maximum of about 90× overall

Speedup grows linearly with cores, so infinite cores give effectively unbounded speedup

Speedup equals the number of cores divided by ten, so it keeps rising with no fixed limit

Speedup is bounded by 1/(serial fraction), giving a maximum of 10×

The predictor stalls the pipeline until the condition resolves, and a flush is when cache lines holding the branch target are evicted to RAM

The predictor guesses the branch outcome to keep fetching; on a wrong guess the wrongly-fetched instructions are discarded in a flush

The predictor caches recent branch results in registers, and a flush is when the operating system forces a context switch mid-instruction

The predictor computes the branch target early using the ALU, and a flush occurs whenever two instructions need the same register at once

Immediate embeds a constant, register indirect uses a register as a pointer, and displacement adds an offset to a register, best for arrays

Immediate uses a register value, register indirect embeds a constant, and displacement dereferences a pointer twice, the last is ideal for arrays

Immediate reads from a fixed address, register indirect adds two registers, and displacement stores a pointer in memory, best used for arrays

Immediate points to the stack, register indirect adds a scaled index, and displacement holds an absolute address, displacement suits arrays best

Time = Instructions × cycle time ÷ CPI; performance improves whenever cycle time grows, because larger cycles do more work per step

Time = Instructions × CPI ÷ cycle time; performance improves whenever CPI drops, since a lower CPI always dominates the final result

Time = Instructions × CPI × cycle time; performance improves only if the CPI reduction outweighs the longer cycle time

Time = Instructions ÷ CPI × cycle time; performance improves only if instruction count also falls to offset the slower clock rate

PC-relative selects registers by numeric offset, aiding loops; indexed scales a constant by operand width, aiding struct fields.

PC-relative loads absolute targets stored near the code, aiding jumps; indexed reads pointers from a fixed table, aiding arrays.

PC-relative dereferences a pointer held in a register, aiding calls; indexed embeds the full target in the instruction, aiding data.

PC-relative adds an offset to the program counter, aiding branches; indexed adds a register to a base, aiding arrays.

They count raw operations without reflecting instruction complexity, ISA differences, or real workload behavior.

They rely on peak theoretical rates that programs rarely hit, plus they say nothing about work done per operation.

They only measure how fast the clock runs and ignore the memory hierarchy and pipeline stalls in the system.

They are computed differently by every vendor, so no two chips can ever be compared on the same numeric basis.

Clock is the bus rate, IPC is the memory latency; a lower clock outperforms when its instruction set is far simpler.

Clock is instructions per second, IPC is cycles per second; a slower clock wins by using shorter pipeline stages.

Clock counts cache hits, IPC counts branch predictions; lower clocks win because they generate far less heat overall.

Clock is cycles per second, IPC is instructions per cycle; higher IPC can beat a faster clock doing less.

RAID 0 mirrors for safety; RAID 1 stripes for speed; RAID 5 duplicates all data twice; RAID 10 uses dedicated parity disks.

RAID 0 stripes with no redundancy; RAID 1 mirrors; RAID 5 stripes with distributed parity; RAID 10 mirrors then stripes.

RAID 0 uses parity blocks; RAID 1 stripes across drives; RAID 5 mirrors every disk; RAID 10 stripes without any redundancy.

RAID 0 stores dual parity; RAID 1 stripes with checksums; RAID 5 mirrors pairs of disks; RAID 10 keeps a single hot spare.

Operating systems could not schedule threads fast enough, so hardware vendors offloaded that work onto multiple parallel cores

Memory latency stopped improving, so extra cores were added purely to hide the growing gap between CPU and RAM speeds

Silicon transistors reached their absolute physical size limit, making any further single-core frequency gains impossible to achieve

Power and heat scale steeply with frequency and voltage, so adding cores became more efficient than pushing clocks higher

The CPU runs untrusted code with elevated kernel privileges, allowing that code to directly read protected memory regions without any checks

The CPU predicts branches wrongly and permanently corrupts register state, which attackers then read out through timing measurements on the bus

The CPU executes instructions ahead of a branch, and side effects on the cache can leak data even after the results are discarded

The CPU reorders memory writes so that stale values remain visible, letting one process silently overwrite another process's private data

Flash can only erase in large blocks, so updating small data forces rewriting whole blocks, causing more physical writes than requested

Flash lacks a spinning platter, so the controller must recompute parity for every logical page and store multiple redundant copies of it

Flash cells slow down as they wear, so the controller duplicates each write across several chips to preserve data before the cells fail

Flash reads are destructive, so every read operation triggers an immediate rewrite of the same page back into the original memory location

Inference must stream huge weight tensors from memory per token, so the GPU idles waiting on data rather than saturating its compute units

The batch size is too large for cache, so the GPU repeatedly recomputes activations rather than fetching them from the slower main memory

The model has so many layers that the GPU runs out of arithmetic units, so extra weights must queue in memory until compute frees up again

Floating-point precision is too high, so the GPU spends most cycles converting formats instead of moving the weight tensors through its cores

It assumes problem size grows with processors, so the parallel share expands and speedup scales nearly linearly.

It assumes communication overhead is negligible, so a fixed workload can be split among unlimited processors freely.

It assumes each processor runs at higher clock speed, so total throughput rises faster than Amdahl's fixed model.

It assumes the serial fraction shrinks to zero with more processors, so speedup grows without any practical bound.

It uses a single parity bit per word that flags any error and then rereads the location until the value stabilizes.

It stores a running checksum per word and, when it differs, recomputes the entire block from surrounding cells.

It duplicates every stored byte and compares copies, so any mismatch is rewritten from the known-good backup copy.

It adds redundant parity bits whose syndrome pinpoints a flipped bit's position, correcting single-bit errors.

Chip cost halves as transistors shrink; its breakdown raised fabrication expense, so vendors froze clock frequency

Transistor count doubles as transistors shrink; its breakdown ended density gains, forcing lower clock frequency

Cache latency stays constant as transistors shrink; its breakdown slowed memory, limiting achievable clock frequency

Power density stays constant as transistors shrink; its breakdown made power per area climb, capping frequency

A four-state counter flips on every outcome, so a single anomalous branch is corrected faster than a slow 1-bit scheme

A four-state counter stores two target addresses, so a single anomalous branch still finds a cached path without stalling

A four-state counter averages the last two outcomes, so a single anomalous branch is smoothed out into one steady guess

A four-state counter needs two consecutive misses to flip, so a single anomalous branch does not cause two mispredicts

A table mapping targets to counters, letting fetch bias toward the most frequently taken path before decoding

A queue holding recently fetched instructions, letting fetch replay them quickly when a branch resolves as taken

A cache mapping branch addresses to targets, giving the next fetch address early before the branch is decoded

A cache mapping branch addresses to outcomes, telling fetch whether a branch will be taken before it is decoded