What does Moore's Law actually state conceptually, and is it still relevant today?
Junior
What does it mean for a processor to be '64-bit'? Specifically, what hardware resources are actually 64 bits wide?
Junior
What is the stored-program concept, and why was it a foundational idea in computer architecture?
Junior
What is an Instruction Set Architecture, and why is it described as the contract between hardware and software?
Junior
Give an overview of the memory hierarchy from registers to secondary storage and explain the latency/capacity/cost trade-offs at each level.
Junior
What is a word in computer architecture, and how does word size relate to the ALU, registers, and data bus width?
Junior
What is the primary difference between RISC and CISC? Why has the industry largely shifted toward RISC-like internals even for CISC ISAs like x86?
Mid
Explain the von Neumann bottleneck. How do modern CPU features like caches and prefetching attempt to mitigate it?
Mid
Explain the difference between von Neumann and Harvard architectures. Why do modern high-performance CPUs often use a 'Modified Harvard' approach?
Mid
What is the conceptual difference between Instruction Set Architecture (ISA) and Microarchitecture (Organization)? Why can two different processors run the same software but have different performance?
Mid
Beyond just 'more memory,' what are the architectural advantages of a 64-bit ISA over a 32-bit ISA (e.g., register pressure, instruction capabilities)?
Mid
What are the fundamental philosophy differences between RISC (like ARM/RISC-V) and CISC (like x86), and why has the industry shifted toward RISC for mobile and increasingly for servers?
Mid
Instruction Set Design
What are the main categories of instructions in a typical ISA (arithmetic/logic, data movement, control flow)?
Junior
What does it mean for an architecture to be 'Load-Store', and how does this differ from an architecture that allows memory operands in arithmetic instructions?
Mid
Explain the difference between a register-based architecture and a stack-based architecture. Which one do modern physical CPUs typically use and why?
Mid
How is an instruction encoded into fields like opcode and operands, and why does encoding design matter?
Mid
How does the hardware stack support procedure calls and returns, and what is a calling convention?
Mid
What are the trade-offs between fixed-length and variable-length instruction sets regarding decoding complexity and code density?
Senior
What is microcode, and why do modern x86 processors translate complex instructions into micro-operations?
Senior
What is VLIW architecture, and how does it differ from superscalar out-of-order execution in exploiting instruction-level parallelism?
Senior
Data Representation & Arithmetic
Explain the difference between Big-Endian and Little-Endian. In what scenario would a software engineer need to be explicitly aware of the underlying hardware's endianness?
Junior
What is Two's Complement, and why is it preferred over Sign-Magnitude for representing signed integers in hardware?
Junior
What is integer overflow, and what happens at the hardware level when a signed integer addition overflows?
Junior
What is the difference between one's complement and two's complement representations?
Junior
Explain why 0.1 + 0.2 does not equal 0.3 in most systems. How does the IEEE-754 standard represent a floating-point number (sign, exponent, mantissa)?
Mid
How does hardware distinguish between signed and unsigned integers, and how does that affect comparison and arithmetic instructions?
Mid
How does IEEE-754 represent special values like NaN, positive/negative infinity, and denormalized (subnormal) numbers?
Mid
What is the exponent bias in IEEE-754, and why is a biased representation used for the exponent?
Mid
When would you use fixed-point arithmetic instead of floating-point, and what are the hardware-level trade-offs in terms of complexity and speed?
Senior
What are the different IEEE-754 rounding modes, and why does rounding matter for numerical accuracy?
Senior
Digital Logic & Datapath
What is the conceptual difference between throughput and latency, and why can optimizing one hurt the other?
Junior
What is the difference between combinational and sequential logic circuits?
Junior
What is a multiplexer, and how is it used in a CPU datapath?
Junior
What is an ALU, and what basic operations does it perform in the datapath?
Junior
What is a register file, and how is it accessed during instruction execution?
Junior
What is the difference between a latch and a flip-flop, and why do synchronous designs prefer flip-flops?
Mid
What is propagation delay, and how does it determine the maximum clock frequency of a circuit?
Mid
What role does the clock signal play in a synchronous processor, and what is clock skew?
Mid
What is the difference between a hardwired control unit and a microprogrammed (microcode) control unit?
Mid
What is the difference between a single-cycle and a multi-cycle datapath, and what are the trade-offs?
Mid
Pipelining & Hazards
Walk through the classic 5-stage RISC pipeline (Fetch, Decode, Execute, Memory, Write-back). What happens at each stage?
Junior
What are the three types of pipeline hazards? Provide a specific example of a 'Data Hazard' and how the hardware resolves it using 'Forwarding' (Bypassing).
Mid
Explain the concept of instruction pipelining. How does it improve throughput without necessarily decreasing latency?
Mid
How does 'forwarding' (or bypassing) resolve a Read-After-Write (RAW) data hazard?
Mid
If you increase the number of pipeline stages, how does it typically affect instruction latency versus instruction throughput?
Mid
What is a 'Pipeline Bubble' (Stall), and what are the performance trade-offs of stalling versus using branch prediction?
Mid
Instruction Level Parallelism
What is the difference between a simple pipelined processor and a superscalar processor?
Mid
Explain the role of the Reorder Buffer (ROB) in an Out-of-Order processor. How does the CPU ensure that instructions commit in the correct program order even if they execute out of order?
Senior
Why do modern CPUs use Register Renaming? How does it help eliminate False Dependencies (WAR/WAW hazards)?
Senior
What is the difference between 'In-Order' and 'Out-of-Order' execution? What hardware structures (like the Reorder Buffer) are required for Out-of-Order execution?
Senior
What is the goal of Out-of-Order execution, and how does the CPU ensure that the final result is the same as if the instructions ran in order?
Senior
How does Tomasulo's algorithm (or a scoreboard) enable dynamic scheduling of instructions?
Senior
Memory Hierarchy & Caches
Explain the Principle of Locality. How do Temporal and Spatial locality influence the design of CPU caches?
Junior
What is a cache line, and why is it usually 64 bytes rather than just a single word?
Junior
What is the difference between a Write-Through and a Write-Back cache policy? When would you choose one over the other?
Mid
Compare Direct-Mapped, Fully-Associative, and Set-Associative caches. What are the trade-offs regarding hit time and miss rate?
Mid
Explain the '3 C's' of cache misses (Compulsory, Capacity, Conflict). How can a software engineer reduce conflict misses?
Mid
What is Average Memory Access Time (AMAT), and how do you compute it across a multi-level cache hierarchy?
Mid
Compare cache replacement policies like LRU, FIFO, and random. What are the trade-offs of implementing true LRU in hardware?
Mid
What is the difference between write-allocate and no-write-allocate policies on a write miss?
Mid
What is the difference between a split cache and a unified cache, and why are L1 caches often split into instruction and data caches?
Mid
Explain how a physical address is broken into tag, index, and offset fields for a set-associative cache.
Mid
What are prefetching and hardware prefetchers, and how do they help hide memory latency?
Mid
What is the difference between an inclusive and an exclusive cache hierarchy?
Senior
Virtual Memory & Address Translation
What is the role of the TLB in the memory hierarchy? What happens during a TLB miss versus a Page Fault?
Mid
What is a Page Fault? Walk through what happens at the hardware level when one occurs.
Mid
How does the MMU use a Page Table to translate a virtual address to a physical address?
Mid
What is a TLB, and how does it interact with the L1 cache (e.g., VIPT vs. PIPT)?
Senior
When a TLB miss occurs, how does the hardware (MMU) find the correct physical address? Explain the concept of a multi-level page table.
Senior
Explain the difference between Virtually Indexed, Physically Tagged (VIPT) and Physically Indexed, Physically Tagged (PIPT) caches. Why does this matter for speed?
Senior
Memory Alignment & Technologies
What are the differences between ROM, PROM, EPROM, EEPROM, and flash memory?
Junior
What is the 'Memory Wall,' and why is the gap between CPU speed and DRAM latency a major bottleneck in modern architecture?
Mid
What is memory alignment, and why do processors often require data to be aligned to specific byte boundaries? What is the performance penalty of an unaligned access?
Mid
Why do we use SRAM for caches but DRAM for main memory? Explain the physical/architectural difference (transistors vs. capacitors).
Mid
What is structure padding, and how does the compiler add padding to satisfy alignment requirements?
Mid
Why does DRAM require periodic refresh, and how does this affect memory performance and power?
Mid
What is memory interleaving, and how do multiple channels and banks improve memory bandwidth?
Senior
Io & Buses
What is the system bus, and what are the roles of the address bus, data bus, and control bus?
Junior
What is DMA (Direct Memory Access)? Why is it more efficient than 'Programmed I/O' for transferring large blocks of data?
Mid
What are the trade-offs between using interrupts vs. polling for I/O operations, and in what specific hardware scenario would polling be more efficient?
Mid
What is the difference between Memory-Mapped I/O and Port-Mapped I/O? How does the CPU distinguish an I/O access from a memory access in MMIO?
Mid
What is the difference between a Trap, an Interrupt, and an Exception from the perspective of the CPU?
Mid
What is bus arbitration, and why is it needed when multiple devices want to use a shared bus?
Mid
What is interrupt vectoring, and how does the CPU find the correct handler when an interrupt occurs?
Mid
Parallelism & Multiprocessing
Briefly explain the four classifications in Flynn's Taxonomy (SISD, SIMD, MISD, MIMD).
Junior
What is the difference between a multicore processor and a multiprocessor (multi-socket) system?
Junior
What is Simultaneous Multithreading (Hyper-threading)? How does it differ from having two physical CPU cores?
Mid
Explain Flynn’s Taxonomy. What is the difference between SIMD and MIMD, and where is each typically used?
Mid
Explain SIMD (Single Instruction, Multiple Data). How does it differ from standard multithreading, and what kind of software tasks benefit most from it?
Mid
What is the difference between shared-memory and distributed-memory parallel architectures?
Mid
How does a GPU achieve high throughput through massive parallelism, and how does its architecture differ from a CPU?
Mid
Explain the difference between UMA and NUMA architectures. How does NUMA affect software performance in large-scale server environments?
Senior
Cache Coherence & Consistency
Explain the MESI protocol. Why is it necessary for maintaining cache coherence in multi-core processors?
Senior
What is 'False Sharing' in a multicore system? How does it occur at the hardware level and how can software be optimized to avoid it?
Senior
What is a memory barrier (or fence) at the hardware level, and why is it necessary for correct synchronization in weakly-ordered memory models?
Senior
What is the difference between snooping-based and directory-based cache coherence, and when is each appropriate?
Senior
How does the MOESI protocol extend MESI, and what does the 'Owned' state add?
Senior
How do hardware atomic operations like compare-and-swap work, and why are they needed for lock-free synchronization?
Senior
What is a hardware memory consistency model, and how does sequential consistency differ from relaxed/weak ordering?
Senior
Virtualization & Protection
What is the difference between privileged (kernel) mode and user mode at the CPU level, and how do protection rings enforce it?
Mid
What hardware state must be saved and restored during a context switch?
Mid
What hardware support enables efficient virtualization, such as Intel VT-x / AMD-V?
Senior
What is an IOMMU, and why is it important for device passthrough and DMA protection in virtualized systems?
Explain the role of the Program Counter and the Instruction Register during the fetch-decode-execute cycle.
Junior
What are the mechanical and performance differences between an HDD and an SSD?
Junior
What is a parity bit, and how does it differ from a checksum for error detection?
Junior
State Amdahl's Law. If 10% of your code is strictly serial, what is the theoretical maximum speedup you can achieve by adding an infinite number of processor cores?
Mid
Why are branches (if/else) expensive for a pipelined processor? Explain how a branch predictor works and what a 'pipeline flush' is.
Mid
Explain the difference between 'Immediate', 'Register Indirect', and 'Displacement' addressing modes. Which one is most commonly used for accessing array elements?
Mid
Explain the CPU Performance Equation. If you decrease the CPI but increase the clock cycle time, under what conditions does the overall performance improve?
Mid
Explain PC-relative and indexed addressing modes and when each is useful.
Mid
Why can metrics like MIPS and FLOPS be misleading when comparing processor performance?
Mid
What is the difference between clock speed and IPC, and why can a processor with a lower clock frequency outperform one with a higher clock?
Mid
Explain the common RAID levels (0, 1, 5, 10) and their trade-offs in performance and redundancy.
Mid
Explain the 'Power Wall.' Why did CPU manufacturers stop aggressively increasing clock speeds around 2005 and move toward multicore designs instead?
Senior
Explain the concept of speculative execution. How can this architectural optimization lead to security vulnerabilities like Spectre or Meltdown?
Senior
How does the physical architecture of an SSD (NAND flash) lead to the 'Write Amplification' effect compared to an HDD?
Senior
In the context of modern AI workloads like LLMs, explain why a model might be 'Memory-Bandwidth Bound' rather than 'Compute Bound'.
Senior
What is Gustafson's Law, and how does it offer a more optimistic view of parallel scalability than Amdahl's Law?
Senior
How does ECC memory detect and correct errors, and what is the idea behind a Hamming code?
Senior
What is Dennard scaling, and how did its breakdown contribute to the end of clock-speed scaling?
Senior
How does a 2-bit saturating counter branch predictor work, and why is it better than a 1-bit predictor?
Senior
What is a Branch Target Buffer (BTB), and what problem does it solve in the fetch stage?
Senior
Top 123 Computer Architecture Interview Questions And Answers 2025 | TechPrep